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ISL22316
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet September 1, 2009 FN6186.2
Low Noise, Low Power I2CTM Bus, 128 Taps
The ISL22316 integrates a single digitally controlled potentiometer (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up, the device recalls the contents of the DCP's IVR to the WR. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 128 resistor taps * I2C serial interface - Two address pins, up to four devices/bus * Non-volatile storage of wiper position * Wiper resistance: 70 typical @ VCC = 3.3V * Shutdown mode * Shutdown current 5A max * Power supply: 2.7V to 5.5V * 50k or 10k total resistance * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T +55C * 10 Ld MSOP or 10 Ld TDFN package * Pb-free (RoHS compliant)
Pinouts
ISL22316 (10 LD MSOP) TOP VIEW
SCL SDA A1 A0 SHDN 1 2 3 4 5 10 9 8 7 6 VCC RH RW RL GND SCL SDA A1 A0 SHDN
ISL22316 (10 LD TDFN) TOP VIEW
1O 2 3 4 5 10 VCC 9 RH 8 RW 7 RL 6 GND
Ordering Information
PART NUMBER (Note) ISL22316UFU10Z* ISL22316WFU10Z* ISL22316UFRT10Z* ISL22316WFRT10Z* PART MARKING 316UZ 316WZ 316U 316W RESISTANCE OPTION (k) 50 10 50 10 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 10 Ld MSOP 10 Ld MSOP 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN PKG. DWG. # M10.118 M10.118 L10.3x3B L10.3x3B
*Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22316 Block Diagram
VCC
SCL SDA A0 A1 I2C INTERFACE
POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH
WR
RW
RL SHDN NON-VOLATILE REGISTERS
GND
Pin Descriptions
MSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 TDFN PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME SCL SDA A1 A0 SHDN GND RL RW RH VCC DESCRIPTION Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device address input for the I2C interface Device address input for the I2C interface Shutdown active low input Device ground pin "Low" terminal of DCP "Wiper" terminal of DCP "High" terminal of DCP Power supply pin
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125C ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Lead MSOP (Note 2). . . . . . . . . . . . 162 N/A 10 Lead TDFN (Notes 3, 4) . . . . . . . . . 74 7 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40C to +125C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -1V for all pins. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions, unless otherwise stated. TEST CONDITIONS W option U option MIN (Note 19) TYP (Note 5) 10 50 -20 W option U option 50 80 70 0 10/10/25 Voltage at pin from GND to VCC 0.1 1 200 VCC +20 MAX (Note 19) UNIT k k % ppm/C (Note 18) ppm/C (Note 18) V pF A
PARAMETER RH to RL Resistance
RH to RL Resistance Tolerance End-to-End Temperature Coefficient
RW VRH, VRL CH/CL/CW (Note 18) ILkgDCP
Wiper Resistance VRH and VRL Terminal Voltages Potentiometer Capacitance Leakage on DCP Pins
VCC = 3.3V, wiper current = VCC/RTOTAL VRH and VRL to GND
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 10) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) Integral Non-linearity Differential Non-linearity Zero-scale Error Monotonic over all tap positions, W and U option Monotonic over all tap positions, W and U option W option U option Full-scale Error W option U option DCP register set to 40 hex for W and U option -1 -0.5 0 0 -5 -2 1 0.5 -1 -1 4 1 0.5 5 2 0 0 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) ppm/C
TCV Ratiometric Temperature Coefficient (Notes 11, 18)
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Analog Specifications
SYMBOL Over recommended operating conditions, unless otherwise stated. (Continued) TEST CONDITIONS MIN (Note 19) TYP (Note 5) MAX (Note 19) UNIT
PARAMETER
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 15) RDNL (Note 14) Integral Non-linearity DCP register set between 10 hex and 7F hex; monotonic over all tap positions; W and U option W option U option Roffset (Note 13) Offset W option U option -1 1 MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12)
Differential Non-linearity
-1 -0.5 0 0 1 0.5
1 0.5 5 2
Operating Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (Volatile Write/Read) TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC Supply Current (Non-volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC Current (Standby) VCC = +5.5V @ +85C, I2C interface in standby state VCC = +5.5V @ +125C, I2C interface in standby state VCC = +3.6V @ +85C, I2C interface in standby state VCC = +3.6V @ +125C, I2C interface in standby state ISD VCC Current (Shutdown) VCC = +5.5V @ +85C, I2C interface in standby state VCC = +5.5V @ +125C, I2C interface in standby state VCC = +3.6V @ +85C, I2C interface in standby state VCC = +3.6V @ +125C, I2C interface in standby state ILkgDig tDCP (Note 18) tShdnRec (Note 18) Leakage Current, at Pins A0, A1, SHDN, SDA and SCL DCP Wiper Response Time DCP Recall Time from Shutdown Mode Voltage at pin from GND to VCC, SDA is inactive SCL falling edge of last bit of DCP data byte to wiper new position From rising edge of SHDN signal to wiper stored position and RH connection SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 0.2 VCC above Vpor, to DCP Initial Value Register recall completed and I2C Interface in standby state 3 -1 1.5 1.5 1.5 2.6 3 5 7 3 5 3 5 2 4 1 mA A A A A A A A A A s s s V V/ms ms MIN (Note 19) TYP (Note 5) MAX (Note 19) 0.5 UNIT mA
VCCRamp VCC Ramp Rate tD Power-up Delay
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Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 5) MAX (Note 19) UNIT
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 17) Non-volatile Write Cycle Time Temperature T +55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECIFICATIONS VIL VIH A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage -0.3 0.7*VCC 0.05*VCC 0 10 400 Any pulse narrower than the max spec is suppressed 50 900 1300 0.4 0.3*VCC VCC + 0.3 V V V V pF kHz ns ns ns
Hysteresis SDA and SCL Input Buffer Hysteresis VOL Cpin (Note 18) fSCL tsp tAA tBUF SDA Output Buffer LOW Voltage, Sinking 4mA A1, A0, SHDN, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO tHD:STO tDH
STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600 1300 0
ns ns ns
tR tF Cb
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL
20 + 0.1*Cb 20 + 0.1*Cb 10
250 250 400
ns ns pF
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Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL Rpu PARAMETER TEST CONDITIONS MIN (Note 19) 1 TYP (Note 5) MAX (Note 19) UNIT k
SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k~2.5k For Cb = 40pF, max is about 15k~20k A1 and A0 Setup Time A1 and A0 Hold Time Before START condition After STOP condition
tSU:A tHD:A NOTES:
600 600
ns ns
5. Typical values are for TA = +25C and 3.3V supply voltage. 6. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 - VCC]/LSB. 9. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i - (i * LSB) - V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 11. TC = --------------------------------------------------------------------------------------------- x -------------------- for i = 16 to 127 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW127 - RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 14. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 127. 15. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 127.
6 for i = 16 to 127, T = -40C to +125C. Max() is the maximum value of the resistance and Min () is [ Max ( Ri ) - Min ( Ri ) ] 10 TC R = --------------------------------------------------------------- x -------------------- the minimum value of the resistance over the temperature range. [ Max ( Ri ) + Min ( Ri ) ] 2 +165C 17. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle.
16.
18. Limits should be considered typical and are not production tested. 19. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
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SDA vs SCL Timing
tF tHIGH tLOW tR tsp tHD:STO
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0 and A1 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A0, A1 tHD:A
Typical Performance Curves
100 90 WIPER RESISITANCE () 80 70 ISB (A) 60 50 40 30 20 10 0 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) VCC = 3.3V, T = +20C VCC = 3.3V, T = -40C 0.2 0 2.7 1.0 0.8 0.6 0.4 T = +25C T = +125C VCC = 3.3V, T = +125C 1.4 1.2
3.2
3.7
4.2 VCC (V)
4.7
5.2
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FIGURE 2. STANDBY ICC vs VCC
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0.2 T = +25C VCC = 2.7V 0.1 DNL (LSB) INL (LSB) 0.1 VCC = 2.7V
(Continued)
0.2 T = +25C
0
0
-0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL)
-0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
1.3 10k 1.1 0.9 ZSERROR (LSB) 0.7 0.5 0.3 0.1 -0.1 -0.3 -40 -20 0 20 50k VCC = 2.7V VCC = 5.5V ZSERROR (LSB)
0.0
-0.3
VCC = 2.7V
50k
VCC = 5.5V
-0.6
-0.9 10k -1.2
40
60
80
100
120
-1.5 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSERROR vs TEMPERATURE
FIGURE 6. FSERROR vs TEMPERATURE
0.4 T = +25C 0.2 DNL (LSB) VCC = 5.5V
0.4 T = +25C 0.2 INL (LSB) VCC = 5.5V
0
0
-0.2
-0.2
-0.4 VCC = 2.7V -0.6 16 36 56 76 96 116
-0.4 VCC = 2.7V -0.6 16 36 56 76 96 TAP POSITION (DECIMAL) 116
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
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ISL22316 Typical Performance Curves
1.0 END TO END RTOTAL CHANGE (%)
(Continued)
105 90
0.5 VCC = 2.7V 0.0 VCC = 5.5V 10k -0.5 50k TCv (ppm/C)
75 60 45 30 15 50k 10k
-1.0 -40
0 -20 0 20 40 60 80 100 120 16 36 56 76 96 TEMPERATURE (C) TAP POSITION (DECIMAL)
FIGURE 9. END-TO-END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
INPUT 300 250 TCr (ppm/C) 200 150 50k 100 50 0 16 10k
OUTPUT
WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5k 36 56 76 96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
SCL
SIGNAL AT WIPER (WIPER UNLOADED)
SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FIGURE 14. LARGE SIGNAL SETTLING TIME
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ISL22316 Pin Description
Potentiometers Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL22316 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RH and shorts RW to RL. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically AND with the SHDN bit in the ACR register. The I2C interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation.
RH
address serial data stream must match with the Address input pins in order to initiate communication with the ISL22316. A maximum of four ISL22316 devices may occupy the I2C serial bus.
Principles of Operation
The ISL22316 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22316 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the I2C serial interface as described in the following sections.
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. DEVICE ADDRESS (A1, A0) The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave
Memory Description
The ISL22316 contains one non-volatile 8-bit register, known as the Initial Value Register (IVR), and two volatile 8-bit registers, Wiper Register (WR) and Access Control Register (ACR). Table 1 shows the Memory map of the ISL22316. The
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non-volatile register (IVR) at address 0, contain initial wiper position and volatile registers (WR) contain current wiper position.
TABLE 1. MEMORY MAP ADDRESS 2 1 0 IVR NON-VOLATILE -- Reserved WR VOLATILE ACR
All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22316, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22316 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22316 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22316 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (see Table 4).
Logic values at pins A1 and A0 respectively
The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR<7>) determines whether the access is to wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL SHDN WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR<6>) disables or enables Shutdown mode. This bit is logically AND with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR<5>) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WR or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3. SHDN pin High Low High Low SHDN bit 1 1 0 0 Mode Normal operation Shutdown Shutdown Shutdown
0 (MSB)
1
0
1
0
A1
A0
R/W (LSB)
I2C Serial Interface
The ISL22316 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22316 operates as a slave device in all applications.
TABLE 4. IDENTIFICATION BYTE FORMAT
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ISL22316
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
0 1 0 1 0 A1 A0 0 A C K
0000 A C K A C K
FIGURE 18. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W = 1
A C K
A C K
S AT CO KP
SIGNAL AT SDA
0 1 0 1 0 A1 A0 0 A C K
0000 A C K
0 1 0 1 0 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 19. READ SEQUENCE
12
FN6186.2 September 1, 2009
ISL22316
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22316 responds with an ACK. At this time, the device enters its standby state (see Figure 18). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL22316 responds with an ACK. Then the ISL22316 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and STOP condition) following the last bit of the last Data Byte (see Figure 19). In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again.
13
FN6186.2 September 1, 2009
ISL22316 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L10.3x3B
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A3 b D 0.18
6 INDEX AREA TOP VIEW B
0.25 3.00 BSC
0.30
5, 8 -
D2 E
// 0.10 C 0.08 C
2.23
2.38 3.00 BSC
2.48
7, 8 -
E2 e k
1.49
1.64 0.50 BSC
1.74
7, 8 -
A C SEATING PLANE SIDE VIEW A3
0.20 0.30
0.40 10 5
0.50
8 2 3 Rev. 0 2/06
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
14
FN6186.2 September 1, 2009
ISL22316 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6186.2 September 1, 2009

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